The present invention relates to a semiconductor memory device and a method of controlling a semiconductor memory device, and more particularly to a semiconductor memory device having a plurality of ports and a method of controlling a semiconductor memory device having a plurality of ports.
A multi-port memory device includes a plurality of ports to be used in various application systems. A multi-port memory device is disclosed in Korean Patent Publication Number 2002-50092.
FIG. 1 is a block diagram illustrating a conventional multi-port memory device. Referring to FIG. 1, the multi-port memory device 100 includes a memory core 110 having memory banks 111, 112 and 113 and ports 120, 130, 140 and 150. The port 120 provides data DQ1 received from an external source to the memory core 110 or outputs data that is stored in the memory core 110 to an external source in response to a first external clock signal CLK1, an address signal ADDR1 and a command signal CMD1. The port 130 provides data DQ2 received from an external source to the memory core 110 or outputs data that is stored in the memory core 110 to an external source in response to a second external clock signal CLK2, an address signal ADDR2 and a command signal CMD2. The port 140 provides data DQ3 received from an external source to the memory core 110 or outputs data that is stored in the memory core 110 to an external source in response to a third external clock signal CLK3, an address signal ADDR3 and a command signal CMD3. The port 150 provides data DQ4 received from an external source to the memory core 110 or outputs data that is stored in the memory core 110 to an external source in response to a fourth external clock signal CLK4, an address signal ADDR4 and a command signal CMD4.
FIG. 2 is a block diagram illustrating another conventional multi-port memory device. Referring to FIG. 2, the multi-port memory device 200 includes a memory core 210 having memory banks 211, 212 and 213, ports 220, 230, 240 and 250 and a clock generator 260. The clock generator 260 generates an internal clock signal ICLK based on an external clock signal CLK. The port 220 provides data DQ1 received from an external source to the memory core 210 or outputs data that is stored in the memory core 210 to an external source in response to the internal clock signal ICLK, an address signal ADDR1 and a command signal CMD1. The port 230 provides data DQ2 received from an external source to the memory core 210 or outputs data that is stored in the memory core 210 to an external source in response to the internal clock signal ICLK, an address signal ADDR2 and a command signal CMD2. The port 240 provides data DQ3 received from an external source to the memory core 210 or outputs data that is stored in the memory core 210 to an external source in response to the internal clock signal ICLK, an address signal ADDR3 and a command signal CMD3. The port 250 provides data DQ received from an external source to the memory core 210 or outputs data that is stored in the memory core 210 to an external source in response to the internal clock signal ICLK, an address signal ADDR4 and a command signal CMD4.
In the conventional multi-port memory device 100 shown in FIG. 1, each of the ports 120, 130, 140 and 150 operates in response to one of the clock signals CLK1, CLK2, CLK3 and CLK4 having different frequencies received from an external source. Accordingly, The multi-port memory device 100 having a structure of FIG. 1 needs to have pins for receiving the clock signals CLK1, CLK2, CLK3 and CLK4 from external sources.
In the conventional multi-port memory device 200 shown in FIG. 2, all of the ports 120, 130, 140 and 150 operate in response to the internal clock signal ICLK. Accordingly, there may be limits in adapting the multi-port memory device 200 shown in FIG. 2 for applications operating at different frequencies.
Accordingly, it is necessary to design a multi-port memory device having ports that may operate at various frequencies.